The invention relates generally to semiconductor device fabrication and, in particular, to structures and methods for testing the reliability of a dielectric layer.
Time-dependent dielectric breakdown (TDDB) is a progressive failure mechanism observed in chips. Time-dependent dielectric breakdown occurs over time and may eventually cause the dielectric layer to break down from the extended application of an operating voltage during operation. When a chip is operated for lengthy periods at normal supply voltages, the leakage current increases gradually as defects are accumulated in the dielectric layer. This process may ultimately lead to breakdown of the dielectric layer and failure due to the loss of the electrical insulating properties of the dielectric layer.
Reliability tests are routinely used to estimate an expected lifetime of a dielectric layer so that chip performance can be guaranteed to remain within specification for a predetermined period of time. Lifetimes are typically obtained by extrapolating TDDB data from small test structures to large chip areas. Under operating conditions with normal supply voltages biasing the gate, reliability testing would take an impractically long period of time. Consequently, reliability testing is usually performed by applying excess electrical stress in the form of voltage and/or current on the dielectric layer. The stress promotes the faster accumulation of defects, which may accelerate the breakdown of the dielectric layer. The breakdown of the dielectric layer may be further accelerated by testing at elevated temperatures. The lifetime of the dielectric layer under operating conditions can then be determined from an extrapolation of the results of reliability testing.
Improved methods and test structures for testing the reliability of a dielectric layer are needed.